Most data processing systems include a system interconnect that enables the exchange of data between system components. Typically, at least one of the system components acts as a resource that is shared by other system components, and the system interconnect provides access to the shared resource. For example, the system memory of a personal computer is typically used by most of the components of the personal computer system, and the data bus of the personal computer system provides access to the system memory.
The manner in which the system interconnect and its associated arbitration scheme are defined determines the minimum "access latency" to shared resources of the data processing system, wherein the minimum access latency is the minimum amount of delay between the time when a system component requests access to a shared resource and the time when the system component gains access to that resource. For synchronous system interconnects, access latency is typically expressed in "clock cycles."
Typically, if a first system component is performing a multiple clock cycle access to a shared resource, a second system component will be prevented from accessing the shared resource until the first system component has completed its access. Thus, the second system component remains idle while awaiting access, and the effective access latency for the second component is several clock cycles greater than the minimum access latency. The effective access latency becomes a critical parameter for maximizing the efficiency of data processing systems that include high speed system components because such system components may become idle while awaiting access to the shared resource, and the processing capabilities of such system components may be underutilized. Therefore, it is desirable to provide a system interconnect and associated arbitration scheme that minimize the effective access latency to shared resources.